Dynamic random access memory (DRAM) require periodic refreshing in order to retain data stored by the memory. Typically, DRAM can be refreshed by periodically issuing refresh commands to the memory, or by issuing a “self-refresh” command. For example, refresh commands can be issued in between memory operations, such as between read and write operations. In a self-refresh state, the memory manages refresh operations for itself using self-refresh circuitry until the state is exited by receiving a self-refresh exit command. Self-refresh is often used while the memory is inactive, and no memory operations in process or are pending.
Memory may be arranged in various configurations. One example is arranging a memory area into “ranks” of memory. Generally, the ranks of memory are independently addressable and may be managed separately, for example, ranks of DRAM may be separately refreshed so that one rank may be in operation while another refreshing. In another example, one rank of memory may be in a self-refresh state while another rank is receiving refresh commands (e.g., in between memory operations). Control over the ranks of memory, including self-refresh, is typically through command signals provided to the multi-rank memory, such as chip-select (CS) signals and clock enable (CKE) signals.